Semiconductor integrated circuit

ABSTRACT

A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C1, C2, C3, . . . ), each including gates G extended in the vertical direction, are aligned in the transverse direction to form a standard cell row. A plurality of the standard cell rows are located side by side in the vertical direction to form a standard cell group. Each of the standard cell rows has a terminal standard cell Ce at least one end of the standard cell row. The terminal standard cell Ce includes two or more supplementary gates, each of which is any of a dummy gate and a gate of an inactive transistor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119(a) on JapanesePatent Application No. 2007-68947 filed on Mar. 16, 2007, the entirecontents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor integrated circuitwhich is effective in suppressing the optical proximity effects.

2. Description of the Related Art

The following terms used in the present specification shall have thefollowing meanings.

“Active transistor” refers to a transistor which contributes to adesired function of a circuit using its operational characteristics.“Inactive transistor” refers to a transistor which does not contributeto a desired function of a circuit. Non-uniformity in gate shape ofinactive transistors does not affect the desired function of thecircuit. “Transistor” can refer to any of an active transistor and aninactive transistor.

Typical examples of the inactive transistor include: a P-channeltransistor whose gate potential is fixed to the supply potential, orN-channel transistor whose gate potential is fixed to the groundpotential, and which is maintained in an OFF state (hereinafter,referred to as “off-transistor”); a P-channel transistor whose gatepotential is fixed to the ground potential and whose source and drainpotentials are fixed to the supply potential, or N-channel transistorwhose gate potential is fixed to the supply potential and whose sourceand drain potentials are fixed to the ground potential, and which isemployed as a capacitor between the power supply and the ground(hereinafter, referred to as “capacitance transistor”); a transistorwhose source and drain potentials are fixed to an equal potential suchthat no current flows; and a transistor which serves to maintain thedrain potential equal to the supply potential or ground potential(hereinafter, referred to as “potential-fixing transistor”).

“Gate” refers to part of a transistor formed of polysilicon, or thelike, which is functionally combined with a diffusion region toconstitute the transistor or refers to a “dummy gate” which is not aconstituent of a transistor.

Hereinafter, a transistor, a typical standard cell formed using thetransistor, and a semiconductor integrated circuit formed using thestandard cell are described in this order with reference to thedrawings.

FIG. 15A shows a P-type transistor Tp which is formed by P-typediffusion regions Dp, a gate G, and an N-type well NW. FIG. 15B shows anN-type transistor Tn which is formed by N-type diffusion regions Dn, agate G, and a P-type well PW. The gate G of the transistors, which ismade of materials including polysilicon and other components, issandwiched by the diffusion regions Dp (or Dn). The source and drain ofthe transistors are formed by the diffusion regions Dp (or Dn).Throughout the drawings, the gate width of the gate G is denoted by “W”,and the gate length of the gate G is denoted by “L”. With varying gatewidths W and gate lengths L, a variety of transistor characteristics areacquired as desired.

FIG. 16 shows a standard cell formed using the transistors of FIG. 15Aand FIG. 15B. Referring to FIG. 16, the standard cell C includes: adiffusion region Dbn for supplying a substrate potential to P-typetransistors Tp1 and Tp2, N-type transistors Tn1 and Tn2, and P-typetransistors Tp1 and Tp2; a diffusion region Dbp for supplying thesubstrate potential to the N-type transistors Tn1 and Tn2; a metal lineMvdd for supplying a supply potential to the sources of the P-typetransistors Tp1 and Tp2; a metal line Mvss for supplying a groundpotential to the sources of the N-type transistors Tn1 and Tn2; and anN-type well NW and a P-type well PW. The distance between the gates ofthe transistors is denoted by “S”. It should be noted that the diffusionregions of the transistors, the gate G, gate width W and gate length Lare not indicated in FIG. 16 in order to avoid repeating thedescriptions of FIG. 15. The standard cell C shown in FIG. 16 is atypical standard cell example and, however, various other standard cellsare possible with flexible arrangements and wirings of transistorshaving various shapes.

FIG. 17 shows a semiconductor integrated circuit including a pluralityof standard cells. As shown in FIG. 17, the standard cells (C1, C2, C3,. . . ) are adjacently aligned in a direction perpendicular to thedirection in which the gates of their transistors are extended, therebyforming a standard cell row. (Hereinafter, the direction in which thegates are extended is referred to as “vertical direction” forconvenience of description, and the direction perpendicular to thevertical direction is referred to as “transverse direction”.) Aplurality of such standard cell rows are located side by side in thevertical direction, which are interconnected to one another to realizean LSI having a desired function. In this process, the standard cellsare located such that the N-type wells NW, P-type wells PW, diffusionregions Dbn, diffusion regions Dbp, metal lines Mvdd and metal linesMvss (none of which are shown) of the respective standard cells arecommon among or adjoining between the standard cells and therefore haveshapes extended in the transverse direction without discontinuity.

Hereinafter, disadvantages resulting from non-uniformity in the gatedimensions of the transistors in this semiconductor integrated circuitare described.

The primary factors in variation of propagation delay time in thesemiconductor integrated circuits include the operation supply voltage,temperature, and process variations. The semiconductor integratedcircuits need to be designed such that the operation of the circuits canbe secured even when all the factors in the variation are in the worstconditions. Especially, the gate length of a transistor is an importantfactor in definition of the operation of the transistor, and theinfluence of non-uniformity in the gate lengths constitutes considerablylarge part of the process variations. In recent years, as theminiaturization of transistors has been advanced, the gate length hasbeen further decreasing so that the gate length non-uniformityconstitutes a larger proportion in general. Therefore, the designmargins need to be increased as the variation of the propagation delaytime increase. Thus, it is difficult to provide a high-performancesemiconductor integrated circuit.

In a typical manufacture process of semiconductor integrated circuits,the photolithography step including resist application, exposure anddevelopment, the etching step for patterning of elements with resistmasks, and the resist removal step are repeated to form an integratedcircuit on a semiconductor substrate. The formation process of the gatesof transistors also includes the photolithography step, the etchingstep, and the resist removal step. In exposure at the photolithographystep, pattern dimensions equal to or smaller than the exposurewavelength result in large errors between the layout dimensions definedat the time of designing and the pattern dimensions on a manufacturedsemiconductor substrate due to the optical proximity effects produced bydiffracted light.

In manufacture of a semiconductor integrated circuit, in patterning ofwirings and other elements via drawing or exposure, corrections forimprovement in dimension accuracy of the pattern are indispensable forpreventing occurrence of optical proximity effects. One of thetechniques of correcting the optical proximity effects is OPC (OpticalProximity effect Correction). According to the OPC, a gate lengthnon-uniformity resulting from the optical proximity effects is estimatedfrom the distance between a gate and another gate pattern adjacent tothe gate, and the mask value of a photoresist used for formation of thegate is corrected in advance such that the non-uniformity is compensatedfor, whereby the gate length value of a gate actually formed afterexposure is maintained constant.

On the other hand, the OPC performed on the gate mask candisadvantageously increase the delay of TAT (Turn Around Time) and theamount of process efforts. Especially because the gate pattern has notconventionally been standardized and the gate length and gate intervalare thus varying over a whole chip, the corrections based on the OPCtechnique have been requiring a huge amount of process efforts.

To avoid such a disadvantage, it has been proposed to limit the varietyof gate length and gate interval to one or several optional values inthe layout process. With this proposed solution, the gate length valueof a gate actually formed can be maintained constant by designingcircuits using a limited number of gate length values or inserting dummygates for achieving uniform gate intervals, without gate maskcorrections based on OPC. Thus, non-uniformity in the gate lengths dueto the optical proximity effects can be suppressed.

FIG. 18 shows a standard cell example which is designed to be used whenthe gate length and gate interval are respectively limited to oneoption. In the standard cell of FIG. 18, the transistor gates G1, G2, .. . and G8 have equal gate length L and are located with constant gateintervals S. Namely, to suppress non-uniformity in the gate lengthsamong the gates G2, G3, G6 and G7 of the active transistors due to theoptical proximity effects, the standard cell is furnished with the dummygates G1, G4, G5 and G8 such that the gate intervals and the gatelengths are uniform.

FIG. 19 shows a conventional semiconductor integrated circuit which isdesigned using such standard cells as shown in FIG. 18. Referring toFIG. 19, the standard cells (C1, C2, C3, . . . ) are arranged in thetransverse direction such that the dummy gates are shared at the bordersbetween the standard cells. Since all the active transistors in thesemiconductor integrated circuit have equal gate lengths and same gateintervals, the gate length value of the gates actually formed can bemaintained constant, and therefore, the non-uniformity in the gatelengths due to the optical proximity effects can be suppressed.

Known technology documents, prior to the present application, in the artfields the inventions of the present application relate to are asfollows:

(Patent Document 1) Japanese Laid-Open Patent Publication No. 10-32253

(Patent Document 2) Specification of U.S. Pat. No. 7,137,092

(Patent Document 3) Japanese Laid-Open Patent Publication No. 2007-12855

As described above, the finer dimensions of the transistors have beenaccompanied by shortening of the gate lengths, resulting in largerinfluence of the optical proximity effects due to diffracted light ingate exposure. In addition, the influence of the optical proximityeffects disadvantageously varies according to the patterns surroundingthe gates.

For example, in the semiconductor integrated circuit shown in FIG. 19,the gate of a centrally-located active transistor is accompanied by twoor more neighboring gates located on the both sides. Specifically, thegate Ga, for example, is accompanied by the gates Ga1 and Ga2 on theleft side and by the gates Ga3 and Ga4 on the right side. On the otherhand, the gate of an active transistor located at an end of a standardcell row can be accompanied only by one neighboring gate. For example,the gate Gb is accompanied only by the dummy gate Gb1 on the left side,with no neighboring gate on the other (right) side.

The influence of the optical proximity effects on a gate which islocated at an end of a standard cell row and which is accompanied onlyby one neighboring gate, such as the gate Gb, is greatly different fromthat on a gate which is accompanied by two or more neighboring gates oneach side, such as the gate Ga. Thus, the magnitude of variations in thegate dimensions is greatly different therebetween.

Thus, uniformly performing the correction processes of OPC over thewhole semiconductor integrated circuit allows the existence of a gate inwhich variations in the gate dimensions are not necessarilyappropriately corrected, leading to errors in the circuit operations. Aconceivable alternative solution is separately performing differentcorrections of OPC on a gate which is located at an end of a standardcell row and which is accompanied only by one neighboring gate, but thissolution undesirably entails an increase in time for correction.

SUMMARY OF THE INVENTION

An objective of the present invention is to provide a semiconductorintegrated circuit which entails no increase in the correction time ofOPC and in which non-uniformity in the gate lengths due to the opticalproximity effects is surely suppressed.

The present invention provides a semiconductor integrated circuitincluding a gate group which includes a plurality of gate rows, each ofthe gate rows including gates extended in a first direction and alignedin a second direction which is perpendicular to the first direction, thegate rows being aligned side by side in the first direction, whereineach of the gate rows includes two or more supplementary gates at leastone end of the gate row, the supplementary gate being a dummy gate or agate which is a constituent of an inactive transistor.

According to the present invention, two or more supplementary gates arelocated at at least one end of each gate row. Therefore, even one of thegates of the active transistors closest to this end is surelyaccompanied by two or more neighboring gates at the end of the row.Hence, in this gate, deviation in the gate length from a predetermineddesign value due to the optical proximity effects is suppressed tosubstantially the same level as the gates of the other activetransistors are. Thus, for example, the corrections of OPC are carriedout uniformly over the whole semiconductor integrated circuit, wherebythe non-uniformity in the gate lengths over the whole semiconductorintegrated circuit is appropriately corrected.

The present invention provides a semiconductor integrated circuitincluding a plurality of standard cell rows located side by side in afirst direction, each of the standard cell rows including a plurality ofstandard cells aligned in a second direction which is perpendicular tothe first direction, each of the standard cells including one or moregates extended in the first direction, wherein each of the standard cellrows includes a terminal standard cell at least one end of the standardcell row, the terminal standard cell including two or more supplementarygates, the supplementary gate being a dummy gate or a gate which is aconstituent of an inactive transistor.

According to the present invention, each standard cell row includes aterminal standard cell, which includes two or more supplementary gates,at least one end of the standard cell row. Therefore, even one of thegates of the active transistors closest to this end is surelyaccompanied by two or more neighboring gates at the end of the row.Hence, in this gate, deviation in the gate length due to the opticalproximity effects is suppressed to substantially the same level as thegates of the other active transistors are. Thus, for example, thecorrections of OPC are carried out uniformly over the wholesemiconductor integrated circuit, whereby the non-uniformity in the gatelengths over the whole semiconductor integrated circuit is appropriatelycorrected.

Thus, according to the present invention, in a semiconductor integratedcircuit, as for the gates of all the active transistors which are to besubjected to corrections of the OPC process, the surrounding gatepatterns located adjacent to the gates are limited so that theuniformity in the gate lengths can surely be suppressed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simple illustration of a layout pattern of a semiconductorintegrated circuit according to embodiment 1 of the present invention.

FIG. 2 is a simple illustration of a layout pattern of a terminalstandard cell used in the semiconductor integrated circuit of FIG. 1.

FIG. 3 is a simple illustration of a layout pattern of a terminalstandard cell according to embodiment 2 of the present invention.

FIG. 4 is a simple illustration of a layout pattern of a semiconductorintegrated circuit according to embodiment 3 of the present invention.

FIG. 5 is a simple illustration of a layout pattern of a terminalstandard cell used in the semiconductor integrated circuit of FIG. 4.

FIG. 6 is a simple illustration of another layout pattern example of theterminal standard cell according to embodiment 3 of the presentinvention.

FIG. 7 is a simple illustration of a layout pattern of a semiconductorintegrated circuit designed using the terminal standard cell of FIG. 6.

FIG. 8 is a simple illustration of a layout pattern of a terminalstandard cell according to embodiment 4 of the present invention.

FIG. 9 is a simple illustration of a layout pattern example where theterminal standard cell of FIG. 8 is adjacent to another standard cell.

FIG. 10 is a simple illustration of a layout pattern of a semiconductorintegrated circuit according to embodiment 5 of the present invention.

FIG. 11 is a simple illustration of a layout pattern of a semiconductorintegrated circuit according to embodiment 6 of the present invention.

FIG. 12 is a simple illustration of a layout pattern of a semiconductorintegrated circuit according to embodiment 7 of the present invention.

FIG. 13 is a simple illustration of a layout pattern of a semiconductorintegrated circuit according to embodiment 8 of the present invention.

FIG. 14 shows a layout example of the semiconductor integrated circuit.

FIG. 15A and FIG. 15B are simple illustrations of typical transistorlayout pattern examples.

FIG. 16 is a simple illustration of a standard cell layout pattern.

FIG. 17 is a simple illustration of a layout pattern example of aconventional semiconductor integrated circuit designed using suchstandard cells as shown in FIG. 16.

FIG. 18 is a simple illustration of a layout pattern of a standard cellwith uniform gate lengths and gate intervals.

FIG. 19 is a simple illustration of a layout pattern of a conventionalsemiconductor integrated circuit which is designed using such standardcells as shown in FIG. 18.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, embodiments of the present invention will be described indetail with reference to the drawings.

Embodiment 1

FIG. 1 is a simple illustration of a layout pattern of a semiconductorintegrated circuit according to embodiment 1 of the present invention.FIG. 2 is a simple illustration of a layout pattern of a standard celllocated at an end of a standard cell row (hereinafter, “terminalstandard cell”) used in the semiconductor integrated circuit of FIG. 1.

In the semiconductor integrated circuit of FIG. 1, standard cells (C1,C2, C3, . . . ) are aligned in the transverse direction (seconddirection) to form a standard cell row. Each of the standard cellsincludes one gate G or a plurality of gates G aligned in the transversedirection, the gate G being extended in the vertical direction (firstdirection). Adjoining standard cells share a dummy gate located at theirborder. A plurality of such standard cell rows are located side by sidein the vertical direction to form a standard cell group.

Located at each of the both ends of each standard cell row is theterminal standard cell Ce of FIG. 2. Referring to FIG. 2, the terminalstandard cell Ce features a dummy gate G1 provided as an supplementarygate at the cell border and a dummy gate G0 provided as an supplementarygate adjacent to the dummy gate G1. The other elements of the terminalstandard cell Ce include a diffusion region Dbn for supplying thesubstrate potential to P-type transistors, a diffusion region Dbp forsupplying the substrate potential to N-type transistors, a metal lineMvdd for supplying the supply potential to the sources of the P-typetransistors, a metal line Mvss for supplying the ground potential to thesources of the N-type transistors, an N-type well NW, and a P-type wellPW. The layout of the terminal standard cell Ce of FIG. 2 is for onethat is to be located at the left end of the standard cell row. Byflipping it from left to right, the layout of FIG. 2 is applicable tothe right end of the standard cell row.

In summary, the semiconductor integrated circuit of FIG. 1 includes agate group which includes a plurality of gate rows, and each of the gaterows includes a plurality of gates aligned in the transverse direction,each of the gates being extended in the vertical direction. At the bothends of each gate row, two or more dummy gates are provided assupplementary gates. Gates G2, G6 and G7 are constituents of activetransistors, and gates G0, G1, G3, G4, G5, G8 and G9 are dummy gates. Itshould be noted that in the semiconductor integrated circuit of FIG. 1the gates are aligned with equal intervals but may not necessarily bealigned with equal intervals.

With the terminal standard cells Ce, even the gate of one of the activetransistors in a standard cell row which is closest to an end of thestandard cell row is necessarily accompanied by two or more gates oneach side. In the lowermost standard cell row of FIG. 1, for example,the gate G2, which is the leftmost gate of active transistors in therow, is accompanied by the dummy gates G0 and G1 on the left sidebecause of a terminal standard cell Ce1. Thus, the influence of theoptical proximity effects on the gate G2 is suppressed to, for example,the level approximately equivalent to the influence of the opticalproximity effects on the gate G6 which is a constituent of anotheractive transistor. Therefore, non-uniformity in the gate lengths of theactive transistors over the whole semiconductor integrated circuit canbe suppressed.

It should be noted that the structure of FIG. 1 includes the terminalstandard cells Ce at the both ends of each standard cell row, but anyone of the ends of each standard cell row may be provided with theterminal standard cell Ce.

In the present embodiment, the terminal standard cell Ce has two dummygates but may have three or more dummy gates. The present inventorsfound that the effect of suppressing non-uniformity in the gate lengthsdue to the optical proximity effects was sufficiently achieved even withonly two dummy gates. In the case of an extra area available forlocation of still another dummy gate, providing three or more dummygates is more preferable in view of enhancement of non-uniformitysuppression effects.

The supplementary gates located at the ends of a gate row are notlimited to the dummy gates but may be gates of inactive transistorswhich do not contribute to the operation or function of the circuit.

In each gate row, among two or more supplementary gates located at anend of the gate row, it is preferable that the two inner gates havelengths in the vertical direction equal to or greater than the length ofthe gate of an active transistor adjacent thereto. Thus, the gate of oneof the active transistors closest to the end of the gate row isaccompanied by two or more neighboring gates which have equal or greaterlengths in the vertical direction. Therefore, whatever gate widths theactive transistors have, non-uniformity in the gate lengths can besuppressed.

In each gate row, the interval between the two or more supplementarygates located at an end of the gate row is preferably equal to theinterval between the innermost supplementary gate and the gate of anactive transistor adjacent thereto. With this feature, the gate of oneof the active transistors in each gate row which is closest to the endof the gate row and the supplementary gates located adjacent thereto areseparated with equal intervals. Thus, non-uniformity in the gate lengthscan further be suppressed.

All the gates of the gate group, including the supplementary gates,preferably have an equal size in the vertical direction. All the gatesof the gate group, including the supplementary gates, preferably have anequal length in the transverse direction. When these two conditions aresatisfied, all the gates including the supplementary gates have an equalgate shape. Thus, non-uniformity in the gate lengths can further besuppressed.

Embodiment 2

FIG. 3 is a simple illustration of a layout pattern of a terminalstandard cell according to embodiment 2 of the present invention. Evenwhen the terminal standard cell CeA of FIG. 3 is employed in thesemiconductor integrated circuit of FIG. 1 in place of the terminalstandard cell Ce, the same effects as those of embodiment 1 areachieved, and namely, non-uniformity in the gate lengths of the activetransistors over the whole semiconductor integrated circuit can besuppressed.

The terminal standard cell CeA of FIG. 3 is different from the terminalstandard cell Ce of FIG. 2 in that the terminal standard cell CeA doesnot have the metal lines Mvdd and Mvss. With this structure, the metalline resources can be secured while non-uniformity in the gate lengthsis suppressed, and the flexibility of circuit designing can be improved.Another conceivable terminal standard cell other than the terminalstandard cell of FIG. 3 does not have the diffusion regions Dbn and Dbp.Namely, a terminal standard cell having two or more dummy gates canproduce the effect of suppressing non-uniformity in the gate lengths.

Embodiment 3

FIG. 4 is a simple illustration of a layout pattern of a semiconductorintegrated circuit according to embodiment 3 of the present invention.FIG. 5 is a simple illustration of a layout pattern of a terminalstandard cell used in the semiconductor integrated circuit of FIG. 4.

In FIG. 4, the terminal standard cells CeB of FIG. 5 are located at theboth ends of each standard cell row in place of the terminal standardcells Ce of FIG. 1. The terminal standard cell CeB shown in FIG. 5 hasfour dummy gates G0 a, G0 b, G1 a and G1 b. The dummy gates G1 a and G1b (first and second supplementary gates) are located at the both endswith respect to the transverse direction of the terminal standard cellCeB. The dummy gate G0 a (third supplementary gate) is adjacent to thedummy gate G1 a. The dummy gate G0 b (fourth supplementary gate) isadjacent to the dummy gate G1 b. It should be noted that, in FIG. 5,illustration of the diffusion regions Dbn and Dbp, metal lines Mvdd andMvss, N-type well NW, and P-type well PW is omitted. Alternatively, theterminal standard cell CeB may not actually have any of these elements.

The semiconductor integrated circuit of FIG. 4 has four dummy gates ateach of the both ends of each gate row. With this structure, the sameeffects as those of embodiment 1 are achieved, and namely,non-uniformity in the gate lengths of the active transistors over thewhole semiconductor integrated circuit can be suppressed.

When the terminal standard cells of FIG. 2 or FIG. 3 are used, theterminal standard cell designed for location at the left end of thestandard cell row need to be flipped from left to right when it islocated at the right end. In contrast, the terminal standard cell CeB ofFIG. 5 has two dummy gates near each of the left and right cell borders.Therefore, the terminal standard cell CeB can be located at any of theleft and right ends of the standard cell row without being flipped.Thus, layout designing of the semiconductor integrated circuit can besimplified.

FIG. 6 is a simple illustration of another layout pattern example of theterminal standard cell according to this embodiment. FIG. 7 is a simpleillustration of a layout pattern of a semiconductor integrated circuitdesigned using the terminal standard cell of FIG. 6. The terminalstandard cell CeC of FIG. 6 includes a dummy gate G0 c in addition tothe components of the terminal standard cell CeB of FIG. 5, namely, fivedummy gates in total. The example with the terminal standard cell CeCalso achieves the same effects as those achieved when the terminalstandard cell CeB of FIG. 5 is used.

Embodiment 4

FIG. 8 is a simple illustration of a layout pattern of a terminalstandard cell according to embodiment 4 of the present invention. Theterminal standard cell CeD shown in FIG. 8 has a gate G0 d in additionto the three dummy gate G0 b, G1 a and G1 b. The gate G0 d and thediffusion regions form transistors Tp1 and Tn1. The transistors Tp1 andTn1 are transistors which constitute the capacitance and are alsoinactive transistors. It should be noted that, in FIG. 8, illustrationof the diffusion regions Dbn and Dbp, metal lines Mvdd and Mvss, N-typewell NW, and P-type well PW is omitted. Alternatively, the terminalstandard cell CeD may not actually have any of these elements.

Even when the terminal standard cell CeD of FIG. 8 is employed in thesemiconductor integrated circuit of FIG. 1 in place of the terminalstandard cells Ce, the same effects as those of embodiment 1 areachieved, and namely, non-uniformity in the gate lengths of the activetransistors over the whole semiconductor integrated circuit can besuppressed. The terminal standard cell CeD of FIG. 8 includes thetransistors Tp1 and Tn1 which constitute the capacitance and, therefore,can also serve as a decoupling capacitance standard cell between powersupplies.

It should be noted herein that, if gate length L0 of the gate G0 d whichis a constituent of the transistors Tp1 and Tn1 is greater than gatelength L1 of the adjacent gate G1 a, there is a probability thatnon-uniformity in the gate lengths of active transistors included in astandard cell adjacent to the terminal standard cell CeD is adverselyaffected.

FIG. 9 is a simple illustration of a layout pattern example where theterminal standard cell CeD of FIG. 8 is adjacent to the standard cell C1in the semiconductor integrated circuit. Referring to FIG. 9, as for thegate G3 of the active transistor, for example, gate length L3 of thegate G3 is equal to gate lengths L1 and L2 of the two adjacent gates G1a and G2, and gate intervals S1 and S2 of these gates are equal. Withthis structure, deviation in gate length L3 from a predetermined designvalue can be sufficiently minimized. However, as for the gate G2 of theactive transistor, the second closest gate on the left side, i.e., thegate G0 d, has longer gate length L0, and therefore, there is aprobability that deviation in gate length L2 from a predetermined designvalue cannot be sufficiently suppressed.

A countermeasure to this undesirable probability is securing, for a gatehaving a greater length, a slightly longer interval between the gate andan adjoining gate. With this arrangement, increase in deviation which isattributed to the greater gate length can be prevented. For example, inthe example of FIG. 9, gate interval S0 is greater than gate intervalsS1 and S2, and therefore, the adverse effects on deviation in the gatelength of the gate G2 which would be attributed to the gate G0 a havinggreater gate length L0 can be prevented. With such a countermeasure, thegate length deviation suppressing effect can be sufficiently achievedeven when a terminal standard cell which includes a capacitancetransistor is used.

It should be noted herein that the terminal standard cell which also hasanother function is a standard cell including a transistor which formsthe capacitance as described above, but it may be, for example, astandard cell including a transistor which has a supply potential fixingfunction, a standard cell including a diode which serves as the means ofdissipating the charge for the purpose of avoiding breakage of a gatedielectric film, or a standard cell including an off-transistor.

Embodiment 5

FIG. 10 is a simple illustration of a layout pattern of a semiconductorintegrated circuit according to embodiment 5 of the present invention.The semiconductor integrated circuit of FIG. 10 is substantially thesame as that of FIG. 4 except that the terminal standard cells CeB arelocated at positions other than the both ends of the standard cell rows.Referring to FIG. 10, one of the terminal standard cells CeB is locatedin the midst of a standard cell row but provides no adverse effects onadjoining standard cells. Therefore, the terminal standard cell can beemployed in the layout designing of the semiconductor integratedcircuit.

The other designs of terminal standard cells, such as the terminalstandard cells Ce and CeA shown in FIG. 2 and FIG. 3, may also belocated at positions other than the both ends of the standard cell rows.

Embodiment 6

FIG. 11 is a simple illustration of a layout pattern of a semiconductorintegrated circuit according to embodiment 6 of the present invention.The semiconductor integrated circuit of FIG. 11 is substantially thesame as that of FIG. 1 except that the terminal standard cell CeD ofFIG. 8 is located on the left side of each of the first and fourthstandard cell rows. Namely, the semiconductor integrated circuit of FIG.11 includes the terminal standard cells having different structurestogether. Even when such terminal standard cells having differentstructures are provided together, the non-uniformity in the gate lengthscan be suppressed as in the above-described embodiments.

Embodiment 7

FIG. 12 is a simple illustration of a layout pattern of a semiconductorintegrated circuit according to embodiment 7 of the present invention.The semiconductor integrated circuit of FIG. 12 is substantially thesame as that of FIG. 4 except that the terminal standard cells CeB atthe both ends of the respective standard cell rows are aligned in thevertical direction. Namely, the terminal standard cells CeB are locatedat equivalent positions with respect to the transverse direction of thecircuit. Rephrasing in view of the gate groups, the dummy gates at theboth ends of the respective gate rows are located at equivalentpositions with respect to the transverse direction of the circuit sothat they are aligned in the vertical direction.

Thus, the layout region of the semiconductor integrated circuit can berectangular. Therefore, the affinity with layout regions of the othersemiconductor integrated circuits can be improved, and the layout of alarger scale semiconductor integrated circuit can be designed morereadily.

Embodiment 8

FIG. 13 is a simple illustration of a layout pattern of a semiconductorintegrated circuit according to embodiment 8 of the present invention.The semiconductor integrated circuit of FIG. 13 includes a macro cell Rwhich is designed based on different layout specifications from thoseused in designing the standard cell rows. At the borders between themacro cell R and the standard cell rows, the terminal standard cells CeBare located for the purpose of suppressing non-uniformity in the gatelengths in the standard cells.

FIG. 14 shows a layout example of the semiconductor integrated circuit.

Referring to FIG. 14, the typical semiconductor integrated circuitseparately includes an internal circuit region 1 and an I/O region 2.The internal circuit region 1 includes an analog region 4 and a memoryregion 5 in addition to standard cell regions 3A and 3B. It should benoted that the standard cell regions are formed only by standard cells,and the memory region and analog regions, for example, are not formed bystandard cells and therefore do not fall within the standard cellregions.

The gate groups described in the above embodiments are within thestandard cell regions 3A and 3B such that the respective gate rows arealigned in the transverse direction. For example, two or moresupplementary gates located at an end of a gate row are aligned alongthe vertically-extending border edges Y1 and Y2 of the standard cellregion 3A. It should be noted that an arrangement where supplementarygates are aligned along at least one of the vertically-extending borderedges of a standard cell region is within the scope of the presentinvention. As a matter of course, two or more supplementary gates may bealigned along every one of the vertically-extending border edges of astandard cell region.

Also, two or more supplementary gates are aligned at the end of a gaterow along the vertically-extending border edge X of the standard cellregion 3B. The border edge X extends along one of the border edges ofthe internal circuit region 1 which includes the standard cell region3B.

The present invention is applicable to a semiconductor integratedcircuit, or the like, which is incorporated in various electronicdevices.

1-12. (canceled)
 13. A semiconductor integrated circuit, comprising: aplurality of standard cell rows located side by side in a firstdirection, each of the standard cell rows including a plurality ofstandard cells aligned in a second direction which is perpendicular tothe first direction, each of the standard cells including one or moregates extended in the first direction, wherein each of the standard cellrows includes a terminal standard cell at least one end of the standardcell row, the terminal standard cell including two or more supplementarygates, the supplementary gate being a dummy gate or a gate which is aconstituent of an inactive transistor.
 14. The semiconductor integratedcircuit of claim 13, wherein the terminal standard cells in each of thestandard cell rows are located at equivalent positions with respect tothe second direction.
 15. The semiconductor integrated circuit of claim13, wherein each of the standard cell rows includes the terminalstandard cell at each end of the standard cell row.
 16. Thesemiconductor integrated circuit of claim 15, wherein the terminalstandard cell includes: first and second supplementary gates at bothends with respect to the second direction; a third supplementary gateadjacent to the first supplementary gate; and a fourth supplementarygate adjacent to the second supplementary gate.
 17. The semiconductorintegrated circuit of claim 13, wherein at least one of the terminalstandard cells includes a transistor which constitutes a capacitor, atransistor which has a supply potential fixing function, anoff-transistor, or a diode.
 18. The semiconductor integrated circuit ofclaim 13, wherein at least one of the terminal standard cells lacks ametal wire for supplying a supply potential to the semiconductorintegrated circuit or a diffusion region for supplying a substratepotential to the semiconductor integrated circuit.